The disclosed invention relates generally to the digitization of unknown input signals such as voltage or current, and more particularly, to an improved method for multistage continuously integrating charge balancing analog-to-digital (A/D) conversion). An A/D converter can be viewed as consisting of two processes: sampling (conversion of continuous-time signals into sequences of samples) and quantization (conversion of continuously-valued signals or sequences into discretely-valued signals or sequences). Sampling is typically performed by sample-and-hold devices. Quantization is typically performed by quantizers. In some cases, such as continuously integrating charge balancing A/D conversion, sampling and quantization operations are implemented in the same stage.
The resolution or number of distinctive input levels which A/D conversion can represent by different output codes (digits), is limited by conversion errors. A sequence of conversion errors can be viewed as conversion noise. Both sampling and quantization cause conversion noise. Quantization noise is fundamental for an A/D converter as it comes from the very fact of representing continuously-valued signals by discrete levels. Sampling noise can result from switching and other errors. With the sampling performed by sample-and-hold devices, a significant portion of the signal energy can be lost and leads to a reduction in the signal-to-noise ratio and increase in significance of all conversion errors.
Multistage noise shaping conversion is an advanced technique for A/D conversion. Oversampling (sampling at a rate higher than the rate required by the signal bandwidth) in combination with noise shaping provides for shaping of the spectral characteristics of conversion noise in such a way that the major part of the noise energy is shifted outside of the signal bandwidth. In post-conversion digital signal processing, the out-of-band part of the conversion noise can be filtered out.
Most known structures for noise shaping conversion are only applicable to sample data sequences. Multistage noise shaping A/D conversion is generally only suitable for a single-bit conversion (sigma-delta modulation) and requires extremely high oversampling and high conversion rates relative to the signal bandwidth. These factors result in significant sampling noise and high design cost.
FIG. 1 illustrates a typical dual slope, single stage, continuously integrating charge balancing A/D converter. An operational amplifier 111 together with the charge balancing capacitor 115 and resistor 114 act as an integrator. The signal is connected to points 1 and 0. Before the start of the conversion cycle, capacitor 115 is positively charged by the input signal. The timing diagram in FIG. 2 illustrates the start of the conversion cycle at the time T.sub.Start1. At that instant, Control Logic 113 generates a transition edge, Start1, synchronous with one of the edges of the high frequency Clock. The Start1 edge starts counter 117, and switches the switch 116 into position 1 starting the discharge of capacitor 115 through resistor 114. The discharge is driven by the difference between the reference voltage and input signal. The magnitude of discharge current in capacitor 115 due to the reference voltage is larger than the charge current due to the input signal. If the value of the reference voltage is more than twice as large as the largest allowable input signal, it takes less than a half of the conversion period to complete the discharge of capacitor 115. Control Logic 113 generates a transition edge End1 at the instant the voltage on capacitor 115 crosses the zero level and is detected by the zero crossing detector 112. A predetermined number of clock cycles later a stop edge, Stop1, is generated by the control logic 113. The stop edge is synchronous with the high frequency clock and stops the counter 117 and switches the switch 116 into position 0 to stop the discharge of capacitor 115. From the time T.sub.STOP1 till the time T.sub.START1 of the start of the next conversion cycle, the rate of charging of capacitor 115 is proportional only to the input signal.
A typical dual slope A/D converter stage is continuously integrating because the signal is never disconnected from the integrator's input. It is charge balancing since the length of the discharge of the charge balancing capacitor 115 in each conversion cycle tends to maintain the balance between the total charge on the capacitor due to the signal and the total discharge of it due to the reference voltage. The values of the resistor 114 and the charge balancing capacitor 115 can be selected in such a way that the discharge time for full scale signals lasts for many clock cycles resulting in the multibit A/D conversion. If the rate of the repetition of conversion cycles is much higher than the bandwidth of the input signal, the stage acts as an oversampling A/D converter. The process of discharging the charge balancing capacitor and counting the discharging time results in sampling and quantization.
The time interval between the zero crossing event End1, and the stop of the discharge event Stop1 is proportional to the error caused by the counter acting as a quantizer. The charge which is being quantized by counting clock cycles during the discharge of capacitor 115, is proportional to the integral of the input signal. The conversion error in the output data sequence 2 can be found as a difference of the sampling and quantization errors created during the two consecutive conversion cycles.
The conversion noise of the first stage is the sequence of differences of consecutive sampling and quantization errors. This noise is shaped such that the largest portion of the noise energy is shifted to higher frequencies outside of the bandwidth of the input signal whose energy is concentrated in the narrow vicinity of the relatively low frequencies. The out-of-band noise can be filtered out by post-conversion digital signal processing (DSP).
Charge balancing and the counting of clock cycles during the discharge interval replaces conversion of voltages by the more precise time counting and provides for further reduction in unpredictable quantization errors and further improvement in the signal-to-noise ratio. With substantial oversampling, the combination of all the aforementioned features allows nearly complete elimination of the in-band conversion errors by making the total conversion noise lower than analog noise of the front-end operational amplifier 111.
In spite of these advantages, a conventional single stage continuously integrating charge balancing A/D converter has a major drawback. In order to achieve a significant reduction in the conversion noise by the post-conversion DSP, a large oversampling is typically required. Such oversampling can be as large as the quantization noise reduction expected from the post-conversion DSP. Large oversampling (orders of magnitude) can require an equally large increase in the clock rate and substantial increase in the complexity of the design and its cost.